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Daphnis
Provisional Identity
Technical Specifications

System Architecture & Subsystems

The Sega Saturn is renowned for its heterogeneous multi-processor architecture. Daphnis approaches emulation with modular subsystem design, deterministic synchronization, and rigorous adherence to primary hardware references.

STATUS DEFINITIONS:Validated in testsImplemented in partUnder developmentNot yet validated in gameplay

CPU

Master SH-2 (SH7604)

Primary 32-bit RISC processor driving main system state

Implemented in part

Independent custom CPU core implementation with substantial instruction pipeline, exception handling, and direct memory bus coupling.

Key Technical Properties
  • 28.6 MHz operation
  • 16 general 32-bit registers
  • Substantial instruction coverage
  • Exception & interrupt handling

Slave SH-2 (SH7604)

Secondary RISC coprocessor for parallel calculations

Under development

Secondary CPU architecture coupled via internal bus arbitration for mathematics, physics, and rendering support.

Key Technical Properties
  • Dual-CPU symmetric multiprocessing
  • Shared bus arbitration
  • Co-processor synchronization

System / Control

SCU (System Control Unit)

Interrupt controller and 3-level DMA engine

Validated in tests

Central routing hub coordinating hardware interrupts from all internal peripherals (VDP, CD, SMPC) and multi-level direct memory access transfers.

Key Technical Properties
  • Level 0 / 1 / 2 DMA engines
  • Priority interrupt arbiter
  • DSP arithmetic pipeline support

SMPC (System Manager & Peripheral Control)

Power sequencing, RTC, and controller input management

Validated in tests

4-bit microcontroller emulator handling INTBACK queries, real-time clock state, reset vectors, and authentic peripheral command interaction.

Key Technical Properties
  • INTBACK peripheral command protocol
  • RTC registers & backup RAM
  • Region & power management

Memory & Interconnect Bus

Segmented address space with authentic wait states

Implemented in part

Accurate memory map routing across Work RAM High (1MB), Work RAM Low (1MB), BIOS ROM, cartridge space, and hardware I/O registers.

Key Technical Properties
  • Work RAM-H (1MB) & Work RAM-L (1MB)
  • Cache-through & cached mirrors
  • Strict byte, word & longword bus cycles

Storage & Media

CD Block (Hitachi SH-1 Subsystem)

Intelligent CD-ROM controller and transfer pipeline

Implemented in part

Emulation of the dedicated sub-CPU orchestrating spindle control, sector buffer partitioning, sector filtering, and PIO/DMA data stream delivery.

Key Technical Properties
  • HIRQ status and transfer flags
  • Selector & partition buffer system
  • Sector acquisition & filtering
  • PIO data register transfers

DiscImage Subsystem

Storage-agnostic physical media mapping architecture

Validated in tests

High-precision physical media abstraction layer supporting authentic FAD (Frame Address) sector lookups, ISO 9660 directory parsing, and raw disc byte inspection.

Key Technical Properties
  • Deterministic FAD sector calculation
  • ISO 9660 volume and path-table parser
  • Byte-for-byte media validation

Graphics

VDP1 (Video Display Processor 1)

Sprite, polygon, and distorted quad rendering engine

Under development

Command-list driven texture mapping and quadrilateral rasterization processor operating into dual framebuffers.

Key Technical Properties
  • Command table interpreter
  • Textured quad & sprite rasterizer
  • Dual 256KB VRAM framebuffers

VDP2 (Video Display Processor 2)

Multi-layer tile, bitmap, and rotation plane compositing

Under development

Complex background processor supporting multiple simultaneous scrolling planes, affine matrix transforms, color calculation, and transparency blending.

Key Technical Properties
  • 5 background planes (NBG0-3, RBG0)
  • Affine rotation & scaling matrices
  • Per-plane priority and color blending

Audio

SCSP (Yamaha YMF292 / FH1)

32-channel PCM sound processor with integrated DSP

Under development

Audio subsystem featuring 32 programmable audio slots, integrated digital signal processor for effects, and dedicated Motorola 68EC000 sound CPU.

Key Technical Properties
  • 32 independent sound slots
  • FM & PCM playback support
  • Dedicated 68EC000 sound driver bus
Media Ingestion Architecture

DiscImage & Physical Sector Representation

The CD Block subsystem is engineered to decouple physical file packaging from host filesystem assumptions. All addressing operates with deterministic Frame Address (FAD) translation and verified sector extraction.

1. FAD Mapping Accuracy

Verified byte-for-byte exactness against original PAL media images using optical lead-in calculations (FAD = LBA + 150).

2. ISO 9660 Descriptors

Autonomous directory traversal and Primary Volume Descriptor extraction without guest code dependencies.

3. Observer Instrumentation

Non-invasive tracing hooks for sector acquisition, buffer partitioning, and data transfer completion verification.

Architecture — Daphnis Emulator