An Independent Sega Saturn Emulator
“Rebuilding one of gaming's most fascinating architectures through original hardware documentation, careful engineering, and verified execution.”
Daphnis is an independent project dedicated to cycle-faithful modeling of the Sega Saturn. Driven by Hitachi and Sega primary documentation, focused on authentic BIOS execution, storage-agnostic CD transport, and non-synthetic validation.
SUB: SH-1 @ 20.0 MHz
STATE: ORBITAL MODEL
Confirmed Technical Achievements
Distinguishing verified execution milestones observed in authentic BIOS runs from preliminary synthetic stubs.
Original European Sega Saturn BIOS Execution
Demonstrated stable execution through the initial stages of the authentic European Sega Saturn retail BIOS ROM without synthetic shortcuts.
Master SH-2 Architecture & Instruction Coverage
Developed an independent 32-bit RISC core supporting memory addressing modes, delay slot execution semantics, and exception dispatching.
SMPC Handshake & Authentic INTBACK Interaction
Successfully handled asynchronous System Manager communications including continuous INTBACK commands required for peripheral and clock negotiation.
SCU Interrupt Arbiter & Peripheral Signaling
Implemented interrupt arbitration coordinating SMPC, VDP blanking triggers, and CD Block events according to hardware priority levels.
The Sega Saturn Architecture
A complex multi-processor architecture featuring dual SH-2 CPUs, custom VDP graphics coprocessors, and an independent CD Block controller.
Master SH-2 (SH7604)
Primary 32-bit RISC processor driving main system state
Independent custom CPU core implementation with substantial instruction pipeline, exception handling, and direct memory bus coupling.
- 28.6 MHz operation
- 16 general 32-bit registers
Slave SH-2 (SH7604)
Secondary RISC coprocessor for parallel calculations
Secondary CPU architecture coupled via internal bus arbitration for mathematics, physics, and rendering support.
- Dual-CPU symmetric multiprocessing
- Shared bus arbitration
SCU (System Control Unit)
Interrupt controller and 3-level DMA engine
Central routing hub coordinating hardware interrupts from all internal peripherals (VDP, CD, SMPC) and multi-level direct memory access transfers.
- Level 0 / 1 / 2 DMA engines
- Priority interrupt arbiter
SMPC (System Manager & Peripheral Control)
Power sequencing, RTC, and controller input management
4-bit microcontroller emulator handling INTBACK queries, real-time clock state, reset vectors, and authentic peripheral command interaction.
- INTBACK peripheral command protocol
- RTC registers & backup RAM
CD Block (Hitachi SH-1 Subsystem)
Intelligent CD-ROM controller and transfer pipeline
Emulation of the dedicated sub-CPU orchestrating spindle control, sector buffer partitioning, sector filtering, and PIO/DMA data stream delivery.
- HIRQ status and transfer flags
- Selector & partition buffer system
DiscImage Subsystem
Storage-agnostic physical media mapping architecture
High-precision physical media abstraction layer supporting authentic FAD (Frame Address) sector lookups, ISO 9660 directory parsing, and raw disc byte inspection.
- Deterministic FAD sector calculation
- ISO 9660 volume and path-table parser
Disc-to-Memory Acquisition Pipeline
Architectural representation of the authentic sector transfer flow from physical media images into guest Work RAM.
The 32-Bit Dual-CPU Era
Before uniform 3D accelerator pipelines became standard, 1990s 32-bit systems handled rasterization through bespoke coprocessors, distorted quad primitives, and multi-plane background compositing.
Daphnis is engineered to model these hardware characteristics authentically down to bus synchronization and frame timing.
Engineered Independently.
Daphnis is built cleanroom from primary Hitachi and Sega technical manuals. The project explicitly avoids copying internal architectures or source code from existing Saturn emulators.
Read the complete engineering manifestoOriginal Technical Manuals
Hitachi SH7604 hardware manuals and Sega developer documentation serve as the baseline authority for register states and bus behavior.
No Fabricated Progress
No synthetic shortcuts or forced guest execution. Subsystems must naturally negotiate protocols through authentic BIOS code.
Storage Agnostic
Media layer decoupled from physical filesystem assumptions, validated against byte-for-byte optical disc layouts.
Deterministic Diagnostics
Built with deep passive inspection hooks, non-invasive trace collectors, and reproducible test fixtures.